DESCRIPTION
Logic Symbol Truth Table A AN8x ABCDEQ B HHXXX L C Q XXHHX L D XXXXHL All other combinations H E HDL Syntax Verilog .................... AN8x inst_name (Q, A, B, C, D, E); VHDL...................... inst_name: AN8x port map (Q, A, B, C, D, E); Pin Loading Pin Name A B C D E AN82 1.0 1.0 1.0 1.0 1.0 Equivalent Loads AN84 1.0 1.0 1.0 1.0 1.0 AN86 2.1 2.1 2.1 2.1 2.1 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) AN82 AN84 AN86 5.0 5.0 11.0 TBD TBD TBD 9.7 10.4 21.5 a. See page 2-15 for power equation. 3-21 $1 [ ® $0, +* PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Number of Equivalent Loads 1 4 AN82 From: Any Input To: Q tPLH tPHL 0.47 0.42 0.57 0.54 Numb
AMI
