DESCRIPTION
Logic Symbol Truth Table A B AN9x A BCDE FQ C HHHXXX L D Q XXXHHX L E XXXXXHL All other combinations H F Core Logic HDL Syntax Verilog .................... AN9x inst_name (Q, A, B, C, D, E, F); VHDL...................... inst_name: AN9x port map (Q, A, B, C, D, E, F); Pin Loading Pin Name A B C D E F AN92 1.0 1.0 1.0 1.0 1.0 1.0 Equivalent Loads AN94 1.0 1.0 1.0 1.0 1.0 1.0 AN96 2.1 2.1 2.1 2.1 2.1 2.1 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) AN92 5.0 TBD 10.5 AN94 7.0 TBD 11.4 AN96 11.0 TBD 20.0 a. See page 2-15 for power equation. 3-23 $1 [ ® $0, +* PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Number of Equivalent Loads 1 4 AN92
AMI
