ANA6 Datasheet | AMI

Description ANAx is a family of AND-NOR circuits consisting of two 3-input AND gates into a 3-input NOR gate. Logic Symbol Truth Table ANAx A BCDE FGQ C HHHXXXX L Q XXXHHHX L F XXXXXXHL All other binations Core Logic HDL Syntax Verilog ANAx inst_name (Q, A, B, C, D, E, F, G); VHDL inst_name: ANAx port map (Q, A, B, C, D, E, F, G); Pin Loading Pin Name A B C D E F G ANA2 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Equivalent Loads ANA4 1.0 1.0 1.0 1.0 1.0 1.0 1.0 ANA6 2.1 2.1 2.1 2.1 2.1 2.1 2.1 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (n A) EQLpd (Eq-load) ANA2 ANA4 21.1 a. See page 2-15 for power equation. 3-25 $1$[ ® $0,+- PLFURQ &026 - DWH $UUD Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Number of Equivalent...