DESCRIPTION
Logic Symbol Truth Table A ANDx ABCDE FGHQ B C HHHXXXXX L D E Q XXXHHHXX L F XXXXXXHHL G All other combinations H H HDL Syntax Verilog .................... ANDx inst_name (Q, A, B, C, D, E, F, G, H); VHDL...................... inst_name: ANDx port map (Q, A, B, C, D, E, F, G, H); Pin Loading Pin Name A B C D E F G H AND2 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Equivalent Loads AND4 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 AND6 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 3-31 $1'[ $0, +* PLFURQ &026 *DWH $UUD\ Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) AND2 AND4 AND6 6.0 8.0 13.0 TBD TBD TBD 11.9 12.1 22.2 a. See page 2-15 for power equation. ® Core Logic 3-32 ® Propagation Delays (ns) Conditions: TJ = 25°C
AMI
