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CVSS - CMOS Gate Array

General Description

CVSS is the resistive tie-down to the core VSS bus for all cell inputs.

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Datasheet Details

Part number CVSS
Manufacturer AMI
File Size 14.43 KB
Description CMOS Gate Array
Datasheet download datasheet CVSS Datasheet

Full PDF Text Transcription for CVSS (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for CVSS. For precise diagrams, and layout, please refer to the original PDF.

&966 $0,+*  PLFURQ &026 *DWH $UUD Description CVSS is the resistive tie-down to the core VSS bus for all cell inputs. Equivalent Gates ................... 1.0 HDL Syn...

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for all cell inputs. Equivalent Gates ................... 1.0 HDL Syntax Verilog .................... CVSS inst_name (Q); VHDL......................