DESCRIPTION
Logic Symbol Truth Table DC2x E Q3 Q2 S1 Q1 S0 Q0 EN S1 S0 Q0N Q1N Q2N Q3N HXXHHHH L L L LHHH L LHHLHH L H L HH L H L HHHHH L HDL Syntax Verilog .................... DC2x inst_name (Q0N, Q1N, Q2N, Q3N, EN, S0, S1); VHDL...................... inst_name: DC2x port map (Q0N, Q1N, Q2N, Q3N, EN, S0, S1); Pin Loading Pin Name S0 S1 EN Equivalent Loads DC21 DC22 3.2 3.2 3.2 3.2 1.0 4.3 Size And Power Characteristics Cell DC21 DC22 Equivalent Gates 8.0 10.0 Power Characteristicsa Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) TBD 17.8 TBD 20.7 a. See page 2-15 for power equation. 3-45 '& [ ® $0, +* PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Number of Equivalent Loads 1 2 DC21 From: Sx To: QN tPLH tPHL From: EN To: QN tPLH tPHL Number of Equivalent L
AMI
