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Core Logic
$0,+* PLFURQ &026 *DWH $UUD
Description DC3x is a family of three-to-eight line decoder/demultiplexers with active low enable.
Logic Symbol
Truth Table
DC3x
E
Q0 Q1 S2 Q2 S1 Q3 S0 Q4 Q5 Q6 Q7
EN S2 S1 S0 Q0N Q1N Q2N Q3N Q4N Q5N Q6N Q7N HXXXHHHHHHHH L L L L LHHHHHHH L L LHHLHHHHHH L LHLHHLHHHHH L LHHHHHLHHHH LHL LHHHHLHHH L H L HHHHHH L HH L HH L HHHHHH L H L HHHHHHHHHH L
HDL Syntax Verilog .................... DC3x inst_name (Q0N, Q1N, Q2N, Q3N, Q4N, Q5N, Q6N, Q7N, EN, S0, S1, S2); VHDL...................... inst_name DC3x port map (Q0N, Q1N, Q2N, Q3N, Q4N, Q5N, Q6N, Q7N, EN, S0, S1, S2);
Pin Loading
Pin Name
S0 S1 S2 EN
Equivalent Loads
DC31
DC32
5.8 5.7
5.4 5.7
5.3 5.3
1.0 1.
DC31 Datasheet
