DF011 - CMOS Gate Array

AMI

General Description

DF011 is a static, master-slave D flip-flop.

RESET is asynchronous and active low.

Output is unbuffered and changes state on the rising edge of the clock.

📥 Download Datasheet

DF011 cmos gate array by AMI - Datasheet Preview

Datasheet Details

Part number	DF011
Manufacturer	AMI
File Size	31.77 KB
Description	CMOS Gate Array
Datasheet	DF011 Datasheet

📁 Similar Datasheet

Part Number	Description	Manufacturer
DF01	Miniature Glass Passivated Single-Phase Bridge Rectifier	GOOD-ARK
DF01	SINGLE-PHASE GLASS PASSIVATED SILICON BRIDGE RECTIFIER	SEMTECH
DF01	1.0A GLASS PASSIVATED SINGLE PHASE BRIDGE RECTIFIER	WON-TOP
DF01	GLASS PASSIVATED BRIDGE RECTIFIER	JINAN JINGHENG ELECTRONICS
DF01	Silicon Bridge Rectifiers	TGS

Other Datasheets by AMI

Part Number	Description
DF001	CMOS Gate Array
DF002	CMOS Gate Array
DF021	CMOS Gate Array
DF031	CMOS Gate Array

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text

Core Logic ') ® $0,+* PLFURQ &026 *DWH $UUD Description DF011 is a static, master-slave D flip-flop. RESET is asynchronous and active low. Output is unbuffered and changes state on the rising edge of the clock. Logic Symbol Truth Table Pin Loading DF011 DQ C R RN D C Q LXXL HL ↑L HH ↑H H X L NC NC = No Change Equivalent Load D 1.0 C 1.0 RN 1.0 Equivalent Gates ................ 8.0 HDL Syntax Verilog .................... DF011 inst_name (Q, C, D, RN); VHDL...................... inst_name: DF011 port map (Q, C, D, RN); Size And Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation. Value TBD 17.8 Units nA Eq-load Propagation Delays Conditions: TJ = 25°C, VDD = 5.