DESCRIPTION
DF021 is a static, master-slave D flip-flop. SET is asynchronous and active low. Output is unbuffered and changes state on the rising edge of the clock. Logic Symbol Truth Table Pin Loading DF021 DSQ C SN D C Q L XXH HL ↑L HH ↑H H X L NC NC = No Change Equivalent Load D 1.0 C 1.0 SN 2.1 Equivalent Gates ................... 7.0 HDL Syntax Verilog...................DF021 inst_name (Q, C, D, SN); VHDL...................... inst_name: DF021 port map (Q, C, D, SN); Size And Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation. Value TBD 14.5 Units nA Eq-load Propagation Delays Conditions: TJ = 25°C, VDD = 5.0V, Typical Process From Delay (ns) To Parameter 1 Number of Equivalent Loads 258 C Q tPLH tPHL 0.66 0.61 0.69 0.65 SN Q tPLH 0.14 0.17 Delay will vary with input conditions. See page 2-17 for interconnect estimates. 0.79 0.80 0.27 0.87 0.96 0.36
AMI
