DESCRIPTION
SET is asynchronous and active low. Outputs are buffered and change state on the rising edge of the clock. Logic Symbol Truth Table DF10x DSQ C Q SN D C Q QN L XXH L HL ↑ LH HH ↑H L H X L NC NC NC = No Change HDL Syntax Verilog...................DF10x inst_name (Q, QN, C, D, SN); VHDL...................... inst_name: DF10x port map (Q, QN, C, D, SN); Pin Loading Pin Name D C SN DF101 1.0 1.0 2.1 Equivalent Loads DF102 DF104 1.0 1.0 1.0 1.0 2.1 3.2 DF106 1.0 1.0 3.2 Size And Power Characteristics Cell Equivalent Gates Power Characteristicsa Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) DF101 8.0 TBD 17.8 DF102 9.0 TBD 21.0 DF104 13.0 TBD 32.5 DF106 15.0 TBD 39.3 a. See page 2-15 for power equation. 3-57 ') [ ® Core Logic $0, +* PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typ
AMI
