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DF211 - CMOS Gate Array

General Description

DF211 is a static, master-slave, multiplexed scan D flip-flop.

RESET is asynchronous and active low.

Output is unbuffered and changes state on the rising edge of the clock.

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Datasheet Details

Part number DF211
Manufacturer AMI
File Size 33.05 KB
Description CMOS Gate Array
Datasheet download datasheet DF211 Datasheet

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Core Logic ') ® $0,+*  PLFURQ &026 *DWH $UUD Description DF211 is a static, master-slave, multiplexed scan D flip-flop. RESET is asynchronous and active low. Output is unbuffered and changes state on the rising edge of the clock. Logic Symbol DF211 D C SD SE R Q Truth Table C ↑ ↑ ↑ ↑ X L D RN SD SE Q HHX L L HX L XHHH XHLH XLXX XHXX NC = No Change H L H L L NC Pin Loading Equivalent Load C 1.0 D 1.0 RN 1.0 SD 1.0 SE 2.1 Equivalent Gates ................ 11.0 HDL Syntax Verilog .................... DF211 inst_name (Q, C, D, RN, SD, SE); VHDL...................... inst_name: DF211 port map (Q, C, D, RN, SD, SE); Size And Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation. Value TBD 22.