DESCRIPTION
Outputs are buffered and change state on the rising edge of the clock. Logic Symbol DF4Fx DQ C SD SE Q Truth Table C ↑ ↑ ↑ ↑ L D SD SE Q HX L H LXLL XHHH XLHL X X X NC NC = No Change QN L H L H NC HDL Syntax Verilog .................... DF4Fx inst_name (Q, QN, C, D, SD, SE); VHDL...................... inst_name: DF4Fx port map (Q, QN, C, D, SD, SE); Pin Loading Pin Name C D SD SE DF4F1 1.0 1.0 1.0 2.1 Equivalent Loads DF4F2 DF4F4 1.0 1.0 1.0 1.0 1.0 1.0 2.1 2.1 DF4F6 1.0 1.0 1.0 2.1 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) DF4F1 9.0 TBD 21.4 DF4F2 10.0 TBD 24.7 DF4F4 13.0 TBD 34.6 DF4F6 16.0 TBD 42.8 a. See page 2-15 for power equation. 3-91 Core Logic ') )[ ® $0, +* PLFURQ &026 *DWH $UUD\ P
AMI
