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DL021 - CMOS Gate Array

General Description

DL021 is a transparent, unbuffered D latch with active low gate transparency.

SET is active low.

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Datasheet Details

Part number DL021
Manufacturer AMI
File Size 27.98 KB
Description CMOS Gate Array
Datasheet download datasheet DL021 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Core Logic '/ ® $0,+*  PLFURQ &026 *DWH $UUD Description DL021 is a transparent, unbuffered D latch with active low gate transparency. SET is active low. Logic Symbol Truth Table Pin Loading DL021 DSQ G SN GN D Q L XXH H H X NC HL L L H L HH NC = No Change Equivalent Load D 1.0 GN 1.0 SN 1.0 Equivalent Gates ................ 4.0 HDL Syntax Verilog .................... DL021 inst_name (Q, D, GN, SN); VHDL...................... inst_name: DL021 port map (Q, D, GN, SN); Size And Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation. Value TBD 7.5 Units nA Eq-load Propagation Delays Conditions: TJ = 25°C, VDD = 5.0V, Typical Process From Delay (ns) To Parameter 1 Number of Equivalent Loads 258 D Q tPLH tPHL 0.38 0.53 0.