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Description DL031 is a transparent, unbuffered D latches with active low gate transparency. RESET and SET are active low.
Logic Symbol DL031
DSQ G
R
Truth Table SN RN D LLX LHX HLX HHX HH L HHH
NC = No Change
GN Q X IL XH XL H NC LL LH
IL = Illegal
Pin Loading
Equivalent Load
D 1.0 GN 1.0 SN 1.0 RN 1.0
Core Logic
Equivalent Gates ................ 5.0
HDL Syntax Verilog .................... DL031 inst_name (Q, D, GN, RN, SN); VHDL...................... inst_name: DL031 port map (Q, D, GN, RN, SN);
Size And Power Characteristics
Parameter
Static IDD (TJ = 85°C) EQLpd
See page 2-15 for power equation.
Value TBD 8.4
Units nA
Eq-load
Propagation Delays Conditions: TJ = 25°C, VDD = 5.