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Core Logic
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Description DL63x is a family of transparent, buffered D latches with active low gate transparency and without SET or RESET.
Logic Symbol
Truth Table
DL63x DQ G
Q
D GN Q QN L L LH HLHL X H NC NC
NC = No Change
HDL Syntax Verilog .................... DL63x inst_name (Q, QN, D, GN); VHDL...................... inst_name: DL63x port map (Q, QN, D, GN);
Pin Loading
Pin Name D GN
DL631 1.1 1.0
Equivalent Loads
DL632
DL634
1.0 1.0
1.0 1.0
DL636 1.0 1.0
Size And Power Characteristics
Power Characteristicsa
Cell Equivalent Gates
Static IDD (TJ = 85°C) (nA)
EQLpd (Eq-load)
DL631 DL632
5.0 6.0
TBD TBD
12.0 15.3
DL634 DL636
9.0 12.0
TBD TBD
23.7 33.5
a. See page 2-15 for power equation.
DL631 Datasheet
