DESCRIPTION
Logic Symbol Truth Table Pin Loading IDQC0 QC P PADM D PADM QO LL HH PADM Load 4.90 pF HDL Syntax Verilog .................... IDQC0 inst_name (QO, PADM); VHDL...................... inst_name: IDQC0 port map (QO, PADM); Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation. Pad Logic 4-6