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IDTS3 - CMOS Gate Array

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Part number IDTS3
Manufacturer AMI
File Size 17.39 KB
Description CMOS Gate Array
Datasheet download datasheet IDTS3 Datasheet
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Description

IDTS3 is a non-inverting, TTL-level Schmitt input buffer piece.  PLFURQ &026 DWH $UUD Pin Loading PADM Load 4.90 pF HDL Syntax Verilog IDTS3 inst_IDTS3 (QC, PADM); VHDL inst_IDTS3 : IDTS3 port map (QC, PADM); Power Characteristics Parameter Static IDD (TJ = 85°C) EQLpd See page 2-15 for power equation.Value TBD 15.8 Units nA Eq-load Propagation Delays Conditions: TJ = 25°C, VDD = 5.0V, Typical Process De

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