DESCRIPTION
Logic Symbol Truth Table INVx AQ AQ AQ LH HL ® HDL Syntax Verilog .................... INVx inst_name (Q, A); VHDL...................... inst_name: INVx port map (Q, A); Pin Loading Equivalent Loads Pin Name INV1 INV2 INV3 INV4 A 1.0 2.1 3.2 4.2 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) INV1 1.0 TBD 0.6 INV2 1.0 TBD 0.6 INV3 2.0 TBD 1.2 INV4 2.0 TBD 1.2 INV5 3.0 TBD 1.8 INV6 3.0 TBD 1.8 a. See page 2-15 power equation INV5 5.2 INV6 6.3 3-126 ® Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Number of Equivalent Loads INV1 From: A To: Q tPLH tPHL Number of Equivalent Loads 1 0.03 0.12 1 4 0.16 0.22 8 INV2 From: A To: Q tPLH tPHL 0.08 0.09 0.20 0.23 Number of Equivalent Loads 1 11 INV3 From: A To:
AMI
