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ITA2 - CMOS Gate Array

Download the ITA2 datasheet PDF. This datasheet also covers the ITA1 variant, as both devices belong to the same cmos gate array family and are provided as variant models within a single manufacturer datasheet.

General Description

ITAx is a family of non-inverting internal tristate buffers with active low enable.

ITA1 1.0 1.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ITA1-AMI.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number ITA2
Manufacturer AMI
File Size 25.84 KB
Description CMOS Gate Array
Datasheet download datasheet ITA2 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Core Logic ,7$[ $0,+*  PLFURQ &026 *DWH $UUD Description ITAx is a family of non-inverting internal tristate buffers with active low enable. Logic Symbol Truth Table ITAx EN AQ EN AQ EN A Q HXZ LLL L HH Z = High Impedance HDL Syntax Verilog .................... ITAx inst_name (Q, A, EN); VHDL...................... inst_name: ITAx port map (Q, A, EN); Pin Loading Pin Name A EN Q ITA1 1.0 1.7 0.6 Equivalent Loads ITA2 ITA4 1.0 1.0 2.3 3.4 1.2 2.5 ITA6 1.0 4.6 3.7 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) ITA1 2.0 TBD 3.9 ITA2 3.0 TBD 6.7 ITA4 6.0 TBD 12.4 ITA6 8.0 TBD 18.1 a. See page 2-15 for power equation.