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ITE1 - CMOS Gate Array

General Description

ITEx is a family of two-phase inverting internal tristate buffers.

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Datasheet Details

Part number ITE1
Manufacturer AMI
File Size 26.87 KB
Description CMOS Gate Array
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Full PDF Text Transcription for ITE1 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for ITE1. For precise diagrams, and layout, please refer to the original PDF.

Core Logic ,7([ $0,+*  PLFURQ &026 *DWH $UUD Description ITEx is a family of two-phase inverting internal tristate buffers. Logic Symbol Truth Table ITEx A A EN QN E ...

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internal tristate buffers. Logic Symbol Truth Table ITEx A A EN QN E QN EN EN E A QN HLXZ LHLH L HH L L L X IL H H X IL IL = Illegal HDL Syntax Verilog .................... ITEx inst_name (QN, A, E, EN); VHDL...................... inst_name: ITEx port map (QN, A, E, EN); Pin Loading Pin Name A E EN QN ITE1 1.0 0.5 0.6 0.6 Equivalent Loads ITE2 ITE4 2.1 4.3 0.9 2.0 1.1 2.4 1.2 2.5 ITE6 6.4 3.1 3.6 3.8 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) ITE1 1.0 TBD 1.2 ITE2 2.0 TBD 2.3 ITE4 4.0 TBD 4.7 ITE6 6.0 TBD 7.2 a. See page 2-15 for power equation.

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