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Core Logic
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Description MX2x is a family of two-to-one digital multiplexers.
Logic Symbol
Truth Table
MX2x S
|0 Q |1
S I0 I1 Q LLXL LHXH HXL L HXHH
HDL Syntax Verilog .................... MX2x inst_name (Q, I0, I1, S); VHDL...................... inst_name: MX2x port map (Q, I0, I1, S);
Pin Loading
Pin Name
I0 I1 S
MX21 1.0 1.1 2.2
Equivalent Loads
MX22
MX24
1.0 2.1
1.0 2.1
2.2 4.2
MX26 2.1 2.1 4.2
Size And Power Characteristics
Cell MX21
Equivalent Gates 3.0
Power Characteristicsa
Static IDD (TJ = 85°C) (nA)
EQLpd (Eq-load)
TBD
5.9
MX22 MX24 MX26
4.0 7.0 8.0
TBD TBD TBD
7.3 13.0 15.8
a. See page 2-15 for power equation.
MX21 Datasheet
