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Core Logic
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Description MX4x is a family of four-to-one digital multiplexers.
Logic Symbol
MX4x S1 S0
|3 |2 Q |1 |0
Truth Table I0 I1 I2 LXX HXX XLX XHX XXL XXH XXX XXX
I3 S1 S0 XLL XLL XLH XLH XHL XHL L HH HHH
Q L H L H L H L H
HDL Syntax Verilog .................... MX4x inst_name (Q, I0, I1, I2, I3, S0, S1); VHDL...................... inst_name: MX4x port map (Q, I0, I1, I2, I3, S0, S1);
Pin Loading
Pin Name
I0 I1 I2 I3 S0 S1
MX41 1.0 1.0 1.0 1.0 3.3 3.3
Equivalent Loads
MX42
MX44
1.0 1.0
1.0 1.0
1.0 1.0
1.0 1.0
3.3 3.3
2.1 2.1
MX46 1.0 1.0 1.0 1.0 3.3 2.
MX41 Datasheet
