DESCRIPTION
Logic Symbol MX4x S1 S0 |3 |2 Q |1 |0 Truth Table I0 I1 I2 LXX HXX XLX XHX XXL XXH XXX XXX I3 S1 S0 XLL XLL XLH XLH XHL XHL L HH HHH Q L H L H L H L H HDL Syntax Verilog .................... MX4x inst_name (Q, I0, I1, I2, I3, S0, S1); VHDL...................... inst_name: MX4x port map (Q, I0, I1, I2, I3, S0, S1); Pin Loading Pin Name I0 I1 I2 I3 S0 S1 MX41 1.0 1.0 1.0 1.0 3.3 3.3 Equivalent Loads MX42 MX44 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 3.3 3.3 2.1 2.1 MX46 1.0 1.0 1.0 1.0 3.3 2.1 3-151 Core Logic 0; [ $0, +* PLFURQ &026 *DWH $UUD\ Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) MX41 8.0 TBD 15.3 MX42 9.0 TBD 19.9 MX44 11.0 TBD 24.9 MX46 12.0 TBD 23.2 a. See page 2-15 for power equation. Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0
AMI
