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MXI21 - CMOS Gate Array

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Description

MXI2x is a family of inverting two-to-one digital multiplexers.

 PLFURQ &026 DWH $UUD MXI2x S I0 Q I1 S I0 I1 QN L LXH L HX L HX L H HXHL HDL Syntax Verilog MXI2x inst_name (QN, I0, I1, S); VHDL inst_name: MXI2x port map (QN, I0, I1, S); Pin Loadin

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Datasheet Details

Part number MXI21
Manufacturer AMI
File Size 23.64 KB
Description CMOS Gate Array
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Core Logic 0;,[ ® Description MXI2x is a family of inverting two-to-one digital multiplexers. Logic Symbol Truth Table $0,+*  PLFURQ &026 *DWH $UUD MXI2x S I0 Q I1 S I0 I1 QN L LXH L HX L HX L H HXHL HDL Syntax Verilog .................... MXI2x inst_name (QN, I0, I1, S); VHDL...................... inst_name: MXI2x port map (QN, I0, I1, S); Pin Loading Pin Name I0 I1 S MXI21 1.0 1.0 2.2 Equivalent Loads MXI22 MXI24 1.0 1.0 1.0 1.0 2.2 2.1 MXI26 1.0 1.0 2.1 Size And Power Characteristics Cell MXI21 Equivalent Gates 4.0 Power Characteristicsa Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) TBD 7.2 MXI22 MXI24 MXI26 4.0 7.0 8.0 TBD TBD TBD 9.0 13.1 19.3 a. See page 2-15 for power equation.
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