DESCRIPTION
Logic Symbol Truth Table NA2x A B A B Q Q ABQ L LH L HH HLH HH L HDL Syntax Verilog .................... NA2x inst_name (Q, A, B); VHDL...................... inst_name: NA2x port map (Q, A, B); Pin Loading Pin Name A B NA21 1.0 1.0 NA22 2.1 2.1 Equivalent Loads NA23 4.3 4.3 NA24 2.1 2.1 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) NA21 NA22 1.0 2.0 TBD TBD 0.8 1.7 NA23 NA24 NA26 4.0 5.0 6.0 TBD TBD TBD 3.4 10.5 14.8 a. See page 2-15 for power equation. NA26 2.1 2.1 3-159 1$ [ $0, +* PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process NA21 Number of Equivalent Loads From: Any Input To: Q tPLH tPHL Number of Equivalent Loads 1 0.09 0.17 1 2 0.13 0.22 4 NA22 From: Any Input To: Q tPL
AMI
