DESCRIPTION
Logic Symbol Truth Table NA3x A B C A B C Q Q A B CQ L XXH X L XH XXLH HHH L HDL Syntax Verilog .................... NA3x inst_name (Q, A, B, C); VHDL...................... inst_name: NA3x port map (Q, A, B, C); Pin Loading Pin Name A B C NA31 1.0 1.0 1.0 NA32 2.1 2.1 2.1 Equivalent Loads NA33 2.1 2.1 2.1 NA34 2.1 2.1 2.1 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) NA31 2.0 TBD 1.6 NA32 3.0 TBD 2.7 NA33 6.0 TBD 8.3 NA34 6.0 TBD 13.3 NA36 8.0 TBD 16.0 a. See page 2-15 for power equation. NA36 2.1 2.1 2.1 3-161 1$ [ $0, +* PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process NA31 Number of Equivalent Loads From: Any Input To: Q tPLH tPHL Number of Equivalent Loads 1 0.11 0.2
AMI
