DESCRIPTION
Logic Symbol Truth Table NA4x A B C Q D A B C Q D A B CDQ L XXXH X L XXH XX L XH XXXLH HHHH L Core Logic HDL Syntax Verilog .................... NA4x inst_name (Q, A, B, C, D); VHDL...................... inst_name: NA4x port map (Q, A, B, C, D); Pin Loading Pin Name A B C D NA41 1.0 1.0 1.0 1.0 NA42 2.1 2.1 2.1 2.1 Equivalent Loads NA43 2.1 2.1 2.1 2.1 NA44 2.1 2.1 2.1 2.1 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) NA41 2.0 TBD 1.9 NA42 4.0 TBD 3.8 NA43 6.0 TBD 8.7 NA44 NA46 7.0 8.0 TBD TBD 12.4 15.7 a. See page 2-15 for power equation. NA46 2.1 2.1 2.1 2.1 3-163 1$ [ $0, +* PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process NA41 Number of Equivalent Loads From: Any Input To: Q t
AMI
