DESCRIPTION
Logic Symbol NA5x A B C D E A B C D E Q Q Truth Table ABCDEQ L XXXXH X L XXXH XX L XXH XXX L XH XXXXLH HHHHH L Core Logic HDL Syntax Verilog .................... NA5x inst_name (Q, A, B, C, D, E); VHDL...................... inst_name: NA5x port map (Q, A, B, C, D, E); Pin Loading Pin Name A B C D E NA51 1.0 1.0 1.0 1.0 1.0 NA52 1.0 1.0 1.0 1.0 1.0 Equivalent Loads NA53 2.1 2.1 2.1 2.1 2.1 NA54 2.1 2.1 2.1 2.1 2.1 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) NA51 NA52 NA53 NA54 NA56 3.0 4.0 8.0 10.0 12.0 TBD TBD TBD TBD TBD 2.7 7.5 12.4 16.5 21.2 a. See page 2-15 for power equation. 3-165 NA56 2.1 2.1 2.1 2.1 2.1 1$ [ $0, +* PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process NA51 Number of Equivalent Load
AMI
