DESCRIPTION
Logic Symbol NA7x A B C D E F G A B C D E F G Q Q Truth Table A BCDE FGQ L XXXXXXH X L XXXXXH XX L XXXXH XXX L XXXH XXXX L XXH XXXXX L XH XXXXXXLH HHHHHHH L HDL Syntax Verilog .................... NA7x inst_name (Q, A, B, C, D, E, F, G); VHDL...................... inst_name: NA7x port map (Q, A, B, C, D, E, F, G); Pin Loading Pin Name A B C D E F G NA71 2.1 2.1 2.1 2.1 2.1 2.1 2.1 NA72 2.1 2.1 2.1 2.1 2.1 2.1 2.1 Equivalent Loads NA73 2.1 2.1 2.1 2.1 2.1 2.1 2.1 NA74 2.1 2.1 2.1 2.1 2.1 2.2 2.1 NA76 2.1 2.1 2.1 2.1 2.1 2.1 2.1 3-169 Core Logic 1$ [ $0, +* PLFURQ &026 *DWH $UUD\ Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) NA71 12.0 TBD 15.3 NA72 11.0 TBD 19.8 NA73 12.0 TBD 20.5 NA74 12.0 TBD 22.8 NA76 14.0 TBD 26.1 a. See page
AMI
