DESCRIPTION
Logic Symbol NA8x A B C D E F G H A B C D E F G H Q Q Truth Table ABCDE FGH LXXXXXXX XLXXXXXX XXLXXXXX XXXLXXXX XXXXLXXX XXXXXLXX XXXXXXLX XXXXXXXL HHHHHHHH Q H H H H H H H H L HDL Syntax Verilog .................... NA8x inst_name (Q, A, B, C, D, E, F, G, H); VHDL...................... inst_name: NA8x port map (Q, A, B, C, D, E, F, G, H); Pin Loading Pin Name A B C D E F G H NA81 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 NA82 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 Equivalent Loads NA83 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 NA84 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 NA86 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 3-171 Core Logic 1$ [ $0, +* PLFURQ &026 *DWH $UUD\ Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) NA81 6.0 TBD 8.5 NA82 12.0 TBD 20.1 NA83 16.0 TBD 24.5 NA84 16.0
AMI
