DESCRIPTION
Logic Symbol Truth Table NO2x A Q B A Q B ABQ L LH LHL HL L HH L HDL Syntax Verilog .................... NO2x inst_name (Q, A, B); VHDL...................... inst_name: NO2x port map (Q, A, B); Pin Loading Pin Name A B NO21 1.0 1.0 NO22 2.1 2.1 Equivalent Loads NO23 4.1 4.2 NO24 2.1 2.1 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) NO21 NO22 1.0 2.0 TBD TBD 0.9 2.0 NO23 NO24 NO26 4.0 6.0 6.0 TBD TBD TBD 3.9 10.7 11.6 a. See page 2-15 for power equation. NO26 2.1 2.1 3-173 12 [ $0, +* PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process NO21 Number of Equivalent Loads From: Any Input To: Q tPLH tPHL Number of Equivalent Loads 1 0.14 0.13 1 2 0.20 0.17 4 NO22 From: Any Input To: Q tPLH
AMI
