DESCRIPTION
Logic Symbol Truth Table NO4x A B C Q D A B C Q D A B CDQ L L L LH HXXX L XHXX L XXHX L XXXHL Core Logic HDL Syntax Verilog .................... NO4x inst_name (Q, A, B, C, D); VHDL...................... inst_name: NO4x port map (Q, A, B, C, D); Pin Loading Pin Name A B C D NO41 1.0 1.0 1.0 1.0 NO42 1.0 1.0 1.0 1.0 Equivalent Loads NO43 2.1 2.1 2.1 2.1 NO44 2.1 2.1 2.1 2.1 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) NO41 2.0 TBD 2.2 NO42 4.0 TBD 7.0 NO43 6.0 TBD 9.4 NO44 7.0 TBD 11.4 NO46 8.0 TBD 14.1 a. See page 2-15 for power equation. NO46 2.1 2.1 2.1 2.1 3-177 12 [ $0, +* PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process NO41 Number of Equivalent Loads From: Any Input To: Q
AMI
