DESCRIPTION
Logic Symbol NO5x A B C D E A B C D E Q Q Truth Table ABCDE LLLLL HXXXX XHXXX XXHXX XXXHX XXXXH Q H L L L L L Core Logic HDL Syntax Verilog .................... NO5x inst_name (Q, A, B, C, D, E); VHDL...................... inst_name: NO5x port map (Q, A, B, C, D, E); Pin Loading Pin Name A B C D E NO51 1.0 1.0 1.0 1.0 1.0 NO52 1.0 1.0 1.0 1.0 1.0 Equivalent Loads NO53 2.1 2.1 2.1 2.1 2.1 NO54 2.1 2.1 2.1 2.1 2.1 Size And Power Characteristics Cell Equivalent Gates Power Characteristicsa Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) NO51 NO52 3.0 4.0 TBD TBD 3.2 7.6 NO53 NO54 8.0 10.0 TBD TBD 10.7 18.1 NO56 12.0 TBD 17.9 a. See page 2-15 for power equation. 3-179 NO56 2.1 2.1 2.1 2.1 2.1 12 [ $0, +* PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process NO51 Number of Equival
AMI
