ODTSXE12 - CMOS Gate Array

This page provides the datasheet information for the ODTSXE12, a member of the ODTSXE04 CMOS Gate Array family.

Datasheet Summary

Description

ODTSXExx is a family of 4 to 24 mA, non-inverting, TTL-level, tristate output buffer pieces with active low enables and controlled slew rate outputs.

AMI

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ODTSXE12 CMOS Gate Array by AMI - Datasheet Preview — Datasheet preview – ODTSXE12

Datasheet Details

Part number	ODTSXE12
Manufacturer	AMI
File Size	25.87 KB
Description	CMOS Gate Array
Datasheet	ODTSXE12 Datasheet
Additional preview pages of the ODTSXE12 datasheet.

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2'76;([[ ® $0,+* PLFURQ &026 *DWH $UUD Description ODTSXExx is a family of 4 to 24 mA, non-inverting, TTL-level, tristate output buffer pieces with active low enables and controlled slew rate outputs. Logic Symbol Truth Table ODTSXExx EN A SL PADM EN A PADM LL L LH H HX Z HDL Syntax Verilog .................... ODTSXExx inst_name (PADM, A, EN); VHDL...................... inst_name: ODTSXExx port map (PADM, A, EN); Pin Loading Pin Name A (eq-load) EN (eq-load) PADM (pF) ODTSXE04 2.3 6.9 4.94 Power Characteristics Cell Output Drive (mA) ODTSXE04 4 ODTSXE08 8 ODTSXE12 12 ODTSXE16 16 ODTSXE24 24 a. See page 2-15 for power equation. ODTSXE08 2.3 6.9 4.94 Load ODTSXE12 2.3 6.9 4.94 ODTSXE16 2.3 6.9 4.

Published: Mar 12, 2018 |