DESCRIPTION
Logic Symbol Truth Table A ON1x A B CDQ L LXXH B Q XXL LH C All other combinations L D Core Logic HDL Syntax Verilog .................... ON1x inst_name (Q, A, B, C, D); VHDL...................... inst_name: ON1x port map (Q, A, B, C, D); Pin Loading Pin Name A B C D ON11 1.0 1.0 1.0 1.0 Equivalent Loads ON12 ON14 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 ON16 2.1 2.1 2.1 2.1 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) ON11 2.0 TBD 2.3 ON12 4.0 TBD 6.6 ON14 4.0 TBD 7.6 ON16 8.0 TBD 15.7 a. See page 2-15 for power equation. 3-181 21 [ $0, +* PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process ON11 Number of Equivalent Loads From: Any Input To: Q tPLH tPHL Number of Equ
AMI
