DESCRIPTION
Logic Symbol Truth Table A B CDQ A ON3x L LXXH B Q XXLXH C XXXLH D All other combinations L Core Logic HDL Syntax Verilog .................... ON3x inst_name (Q, A, B, C, D); VHDL...................... inst_name: ON3x port map (Q, A, B, C, D); Pin Loading Pin Name A B C D ON31 1.0 1.0 1.1 1.0 Equivalent Loads ON32 ON34 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 ON36 2.1 2.1 2.1 2.1 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) ON31 2.0 TBD 2.6 ON32 4.0 TBD 9.0 ON34 4.0 TBD 6.3 ON36 8.0 TBD 15.8 a. See page 2-15 for power equation. 3-185 21 [ $0, +* PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process ON31 Number of Equivalent Loads From: Any Input To: Q tPLH
AMI
