DESCRIPTION
Logic Symbol Truth Table A ON6x A BCDE FQ B L L LXXXH C Q XXXL L LH D All other combinations L E F Core Logic HDL Syntax Verilog .................... ON6x inst_name (Q, A, B, C, D, E, F); VHDL...................... inst_name: ON6x port map (Q, A, B, C, D, E, F); Pin Loading Pin Name A B C D E F ON62 1.0 1.0 1.0 1.0 1.0 1.0 Equivalent Loads ON64 1.0 1.0 1.0 1.0 1.0 1.0 ON66 2.1 2.1 2.1 2.1 2.1 2.1 Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) ON62 5.0 TBD 9.2 ON64 6.0 TBD 9.8 ON66 12.0 TBD 17.0 a. See page 2-15 for power equation. 3-191 21 [ ® $0, +* PLFURQ &026 *DWH $UUD\ Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical Process Number of Equivalent Loads 1 4 ON62 From: Any Input To: Q tPLH
AMI
