DESCRIPTION
Logic Symbol Truth Table A ONDx B ABCDE FGHQ C D L L LXXXXXH E Q XXXL L LXXH F XXXXXXL LH G All other combinations L H HDL Syntax Verilog .................... ONDx inst_name (Q, A, B, C, D, E, F, G, H); VHDL...................... inst_name: ONDx port map (Q, A, B, C, D, E, F, G, H); Pin Loading Pin Name A B C D E F G H OND2 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Equivalent Loads OND4 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 OND6 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 3-207 21'[ $0, +* PLFURQ &026 *DWH $UUD\ Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) OND2 6.0 TBD 12.4 OND4 8.0 TBD 11.6 OND6 13.0 TBD 21.0 a. See page 2-15 for power equation. Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V, Typical
AMI
