ONE2 Datasheet | AMI

Core Logic 21([ ® $0,+- PLFURQ &026 - DWH $UUD Description ONEx is a family of OR-NAND circuits consisting of three 3-input OR gates into a 3-input NAND gate. Logic Symbol Truth Table A ONEx B ABCDE FGH I Q L L LXXXXXXH E Q XXXL L LXXXH F XXXXXXL L LH All other binations HDL Syntax Verilog .................... ONEx inst_name (Q, A, B, C, D, E, F, G, H, I); VHDL...................... inst_name: ONEx port map (Q, A, B, C, D, E, F, G, H, I); Pin Loading Pin Name A B C D E F G H I ONE2 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Equivalent Loads ONE4 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 ONE6 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 3-209 21([ $0,+- PLFURQ &026 - DWH $UUD Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (n A) EQLpd...