DESCRIPTION
Logic Symbol Truth Table A ONEx B ABCDE FGH I Q C L L LXXXXXXH D E Q XXXL L LXXXH F XXXXXXL L LH G All other combinations L H I HDL Syntax Verilog .................... ONEx inst_name (Q, A, B, C, D, E, F, G, H, I); VHDL...................... inst_name: ONEx port map (Q, A, B, C, D, E, F, G, H, I); Pin Loading Pin Name A B C D E F G H I ONE2 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 Equivalent Loads ONE4 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 ONE6 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 2.1 3-209 21([ $0, +* PLFURQ &026 *DWH $UUD\ Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD (TJ = 85°C) (nA) EQLpd (Eq-load) ONE2 7.0 TBD 13.3 ONE4 8.0 TBD 14.4 ONE6 14.0 TBD 22.4 a. See page 2-15 for power equation. Propagation Delays (ns) Conditions: TJ = 25°C, VDD = 5.0V,
AMI
