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PLU3 - CMOS Gate Array

Description

PLU3 is an active pull-up buffer piece.

 PLFURQ &026 DWH $UUD Truth Table Pin Loading N/A N/A HDL Syntax Verilog PLU3 inst_name (PADM); VHDL inst_name: PLU3 port map (PADM); Power Characteristics Parameter Value Units Static IDD (TJ = 85°C)

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Datasheet Details

Part number PLU3
Manufacturer AMI
File Size 16.52 KB
Description CMOS Gate Array
Datasheet download datasheet PLU3 Datasheet

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® Description PLU3 is an active pull-up buffer piece. Logic Symbol PLU3 PADM 3/8 $0,+*  PLFURQ &026 *DWH $UUD Truth Table Pin Loading N/A N/A HDL Syntax Verilog .................... PLU3 inst_name (PADM); VHDL...................... inst_name: PLU3 port map (PADM); Power Characteristics Parameter Value Units Static IDD (TJ = 85°C) TBD nA EQLpd 149.7 Eq-load See page 2-15 for power equation. Delay will vary with input conditions. See page 2-17 for interconnect estimates.
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