DESCRIPTION
Logic Symbol SLF00x DQ C SD SE SCE Truth Table C ↑ ↑ ↑ ↑ L L L L L H D SD SE SCE Q HXL LH LXLLL XHH L H XLHL L X X X L NC HX LHH LXLHL XHHHH X LHHL X X X H NC NC = No Change HDL Syntax Verilog .................... SLF00x inst_name (Q, C, D, SCE, SD, SE); VHDL...................... inst_name: SLF00x port map (Q, C, D, SCE, SD, SE); Pin Loading Pin Name C D SD SE SCE SLF001 1.0 1.0 1.0 2.1 2.1 Equivalent Loads SLF002 SLF004 1.0 1.0 1.0 1.0 1.0 1.0 2.1 2.1 2.1 2.1 SLF006 1.0 1.0 1.0 2.1 2.1 3-217 Core Logic 6/) [ $0, +* PLFURQ &026 *DWH $UUD\ Size And Power Characteristics Power Characteristicsa Cell Equivalent Gates Static IDD
AMI
