DESCRIPTION
SET is asynchronous and active low. Logic Symbol SLF02x D SQ C SD SE SCE Truth Table SN C D SD SE SCE Q H↑HXL LH H↑LXL L L H ↑ XHH L H H↑XLHL L H L X X X L NC HLHX LHH HL LXLHL HL XHHHH HL X LHHL H H X X X H NC L XXXXXH NC = No Change HDL Syntax Verilog .................... SLF02x inst_name (Q, C, D, SCE, SD, SE, SN); VHDL...................... inst_name:SLF02x port map (Q, C, D, SCE, SD, SE, SN); Pin Loading Pin Name C D SD SE SCE SN SLF021 1.0 1.0 1.0 2.2 2.1 2.1 Equivalent Loads SLF022 SLF024 1.0 1.0 1.0 1.0 1.0 1.0 2.2 2.2 2.2 2.2 2.1 2.1 SLF026 1.0 1.0 1.0 2.2 2.1 2.1 3-226 Core Logic 6/) [ ® $0, +* PLFURQ &026 *DWH $UUD\
AMI
