DESCRIPTION
SET and RESET are asynchronous and active low. Logic Symbol SLF03x S DQ C SD SE SCE R Truth Table RN SN HH HH HH HH HH HH HH HH HH HH HL LX C D SD SE SCE Q ↑HXL LH ↑LXLLL ↑ XHH L H ↑XLHL L L X X X L NC LHX LHH L LXLHL L XHHHH L X LHHL H X X X H NC XXXXXH XXXXXL NC = No Change HDL Syntax Verilog .................... SLF03x inst_name (Q, C, D, RN, SCE, SD, SE, SN); VHDL...................... inst_name: SLF03x port map (Q, C, D, RN, SCE, SD, SE, SN); Pin Loading Pin Name C D RN SD SE SCE SN SLF031 1.0 1.0 2.2 1.0 2.2 2.1 2.1 Equivalent Loads SLF032 SLF034 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 2.2 2.2 2.1 2.1 2.2 2.2 SLF036 1.0 1.0 1.0 1.0 2.2 2
AMI
