A43L0632 Datasheet | AMIC Technology

Features Power supply - VDD: 3.3V VDDQ : 3.3V LVTTL patible with multiplexed address Two banks / Pulse RAS MRS cycle with address key programs - CAS Latency (2 & 3) - Burst Length (1,2,4,8 & full page) - Burst Type (Sequential & Interleave) Clock Frequency (max) : 167MHz @ CL=3 (-6) 143MHz @ CL=3 (-7) 512K X 32 Bit X 2 Banks Synchronous DRAM All inputs are sampled at the positive going edge of the system clock DQM for masking Auto & self refresh 64ms refresh period (4K cycle) Industrial operating temperature range: -40ºC to +85ºC for -U series. Available in 90 Balls CSP (8mm X 13mm) Package is available to lead free (-F series) General Description The A43L0632 is 33,554,432 bits synchronous high data rate Dynamic RAM organized as 2 X 524,288 words by 32 bits, fabricated with AMIC’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. Pin Configuration 90 Balls CSP (8 mm x 13 mm) Top View A B C D E F G H J K L M N P R 1 DQ26 DQ28 VSSQ VSSQ VDDQ VSS A4 A7 CLK DQM1 VDDQ VSSQ VSSQ DQ11 DQ13 90 Ball (8X13) CSP 2 3 7 DQ24 VSS VDD VDDQ VSSQ VDDQ DQ27 DQ25 DQ22 DQ29 DQ30 DQ17 DQ31 NC NC A2 DQM3 A3 A5 A6 A10 A8 NC NC CKE A9 BA NC DQ8 DQ10 DQ12 VDDQ DQ15 NC VSS DQ9 DQ14 VSSQ VSS 8 DQ23 VSSQ DQ20 DQ18 DQ16 DQM2 A0 NC 9 DQ21 DQ19 VDDQ VDDQ VSSQ VDD A1 DQM0 VSSQ VDDQ VDDQ DQ4 DQ2 VDD DQ6 DQ1 VDDQ VDD DQ7 DQ5 DQ3 VSSQ DQ0 PRELIMINARY (August, 2005, Version 0.0) AMIC Technology, Corp. .. Block Diagram LWE I/O Control Bank Select Data Input Register Row Buffer Refresh Counter Row Decoder Output Buffer 512K X 32 Sense...