A43L2632 Datasheet | AMIC Technology

Features JEDEC standard 3.3V power supply LVTTL patible with multiplexed address Four banks / Pulse RAS MRS cycle with address key programs - CAS Latency (2,3) - Burst Length (1,2,4,8 & full page) - Burst Type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Deep Power Down Mode Burst Read Single-bit Write operation Clock Frequency (max) : 166MHz @ CL=3 (-6) 143MHz @ CL=3 (-7) 1M X 32 Bit X 4 Banks Synchronous DRAM DQM for masking Auto & self refresh 64ms refresh period (4K cycle) Self refresh with programmable refresh period through EMRS cycle Programmable Power Reduction Feature by partial array activation during Self-refresh through EMRS cycle 86 Pin TSOP (II) operating temperature range: 0ºC to + 70ºC General Description The A43L2632 is 67,108,864 bits Low Power synchronous high data rate Dynamic RAM organized as 4 X 1,048,576 words by 32 bits, fabricated with AMIC’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. PRELIMINARY (January, 2005, Version 0.0) AMIC Technology, Corp. Pin Configuration TSOP (II) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 WE CAS RAS CS A11 BA0 BA1 A10/AP A0 A1 A2 DMQ2 VDD NC DQ16 VSSQ DQ 17 DQ 18 VDDQ DQ 19 DQ 20 VSSQ DQ 21 DQ 22 VDDQ DQ 23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSS DQM1 NC NC CLK CKE A9 A8 A7 A6 A5 A4 A3 DMQ3 VSS NC DQ31 VDDQ DQ30 DQ29 VSSQ DQ 28 DQ27 VDDQ DQ26 DQ25 VSSQ...