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A67L8318 - 256K X 16/18/ 128K X 32/36 LVTTL/ Pipelined DBA SRAM

Description

The AMIC Direct Bus Alternation™ (DBA™) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.

Features

  • n Fast access time: 4.5/5.0/6.0 ns (117/100/83MHz) n Direct Bus Alternation between READ and WRITE cycles allows 100% bus utilization n Signal +3.3V ± 5% power supply n Individual Byte Write control capability n Clock enable ( CEN ) pin to enable clock and suspend operations n Clock-controlled and registered address, data and control signals n Registered output for pipelined.

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Datasheet Details

Part number A67L8318
Manufacturer AMIC Technology
File Size 272.85 KB
Description 256K X 16/18/ 128K X 32/36 LVTTL/ Pipelined DBA SRAM
Datasheet download datasheet A67L8318 Datasheet
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Full PDF Text Transcription

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A67L8316/A67L8318/ A67L7332/A67L7336 Series 256K X 16/18, 128K X 32/36 Preliminary Document Title 256K X 16/18, 128K X 32/36 LVTTL, Pipelined DBA SRAM Revision History Rev. No. 0.0 0.1 LVTTL, Pipelined DBATM SRAM History Initial issue Change fast access time from 4.0/4.2/4.5/5.0 ns to 4.5/5.0/6.0 ns Issue Date March 11, 1999 December 29, 1999 Remark Preliminary PRELIMINARY (December, 1999, Version 0.1) AMIC Technology, Inc. DBA and Direct Bus Alternation are trademarks of AMIC Technology, Inc A67L8316/A67L8318/ A67L7332/A67L7336 Series 256K X 16/18, 128K X 32/36 Preliminary Features n Fast access time: 4.5/5.0/6.0 ns (117/100/83MHz) n Direct Bus Alternation between READ and WRITE cycles allows 100% bus utilization n Signal +3.
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