A67P9336 Datasheet | AMIC Technology

.. A67P0618/A67P9336 Series Preliminary Document Title 2M X 18, 512K X 36 LVTTL, Pipelined Ze BLTM SRAM Revision History Rev. No. 1M X 18, 512K X 36 LVTTL, Pipelined Ze BLTM SRAM History Initial issue Issue Date September, 20, 2004 Remark Preliminary PRELIMINARY (September, 2004, Version 0.0) AMIC Technology, Corp. A67P0618/A67P9336 Series Preliminary Features Fast access time: 2.6/2.8/3.2/3.5/3.8/4.2 (250/227/200/166/150/133MHz) Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization Signal +2.5V ± 5% power supply Individual Byte Write control capability Clock enable ( CEN ) pin to enable clock and suspend operations Clock-controlled and registered address, data and control signals Registered output for pipelined applications Three separate chip enables allow wide range of options for CE control, address pipelining Internally self-timed write cycle Selectable BURST mode (Linear or Interleaved) SLEEP mode (ZZ pin) provided Available in 100 pin LQFP package 1M X 18, 512K X 36 LVTTL, Pipelined Ze BLTM SRAM General Description The AMIC Zero Bus Latency (Ze BLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. The A67P0618, A67P9336 SRAMs integrate a 1M X 18, 512K X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. The synchronous inputs include all address, all data inputs, active low chip enable ( CE ), two additional chip enables for easy depth expansion (CE2, CE2 ), cycle start input (ADV/ LD ), synchronous clock enable ( CEN ), byte write enables ( BW1, BW2 , BW3 , BW4 ) and read/write (R/ W ). Asynchronous inputs include the output enable ( OE ), clock (CLK), SLEEP mode (ZZ, tied LOW if unused) and...