LP61L1024 Datasheet | AMIC Technology

Features n Single +3.3V power supply n Access times: 12/15 ns (max.) n Current: Operating: 170m A (max.) Standby: 10m A (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL patible n mon I/O using three-state output n Output enable and two chip enable inputs for easy application n Data retention voltage: 2.0V (min.) n Available in 32-pin SOJ 300 mil, 32-pin TSOP and 32pin TSSOP and 36-pin CSP packages General Description The LP61L1024 is a low operating current 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply. Inputs and three-state outputs are TTL patible and allow for direct interfacing with mon system bus structures. Two chip enable inputs are provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2.0V. Product Family Product Family Operating Temperature VCC Range Power Dissipation Speed Data Retention (ICCDR, Typ.) Standby (ISB1, Typ.) Operating (ICC1, Typ.) Package Type 32L SOJ 0°C ~ 70°C 32L TSOP 3V ~ 3.6V 12/15 ns 0.4m A 0.5m A 130m A 32L TSSOP 36B µBGA 1. Typical values are measured at VCC = 3.0V, TA = 25°C and not 100% tested. 2. Data retention current VCC = 2.0V. (August, 2002, Version 2.1) AMIC Technology, Inc. Pin Configurations n SOJ n TSOP / TSSOP n CSP (Chip Size Package) 36-pin Top View NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O8 I/O7 I/O6 I/O5 I/O4 Pin No. Pin Name Pin No. Pin Name 1 A11 17 A3 2 A9 18 A2 3 A8 19 A1 4 A13 20 A0 1 1 A B C D E F G H A0 I/O4 I/O5 GND VCC I/O6 I/O7 A9 OE A10 NC CE1 A11 NC A16 A12 A15 A13 2 A1 A2 3 NC WE NC 4 A3 A4 A5 5 A6 A7 6 A8 I/O0 I/O1 VCC GND I/O2 I/O3 A14 LP61L1024V(X) Block Diagram VCC GND...