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ADSP-21060LC - SHARC Processor

Download the ADSP-21060LC datasheet PDF. This datasheet also covers the ADSP-21060 variant, as both devices belong to the same sharc processor family and are provided as variant models within a single manufacturer datasheet.

General Description

4 SHARC Family Core Architecture 4 Memory and I/O Interface

Key Features

  • 240-lead thermally enhanced MQFP_PQ4 package, 225-ball plastic ball grid array (PBGA), 240-lead hermetic CQFP package RoHS compliant packages KEY.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ADSP-21060-ANALOGDEVICES.pdf) that lists specifications for multiple related part numbers.

Other Datasheets by Analog Devices

Part Number Description
ADSP-21060L SHARC Processor
ADSP-21060 SHARC Processor
ADSP-21060C SHARC Processor
ADSP-21061 Commercial Grade SHARC DSP Microcomputer
ADSP-21061L Commercial Grade SHARC DSP Microcomputer
ADSP-21062 SHARC Processor
ADSP-21062L SHARC Processor
ADSP-21065L DSP Microcomputer
ADSP-2100A DSP Microcomputers
ADSP-2101 DSP Microcomputers

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
SHARC Processor ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC SUMMARY High performance signal processor for communications, graphics and imaging applications Super Harvard Architecture 4 independent buses for dual data fetch, instruction fetch, and nonintrusive I/O 32-bit IEEE floating-point computation units—multiplier, ALU, and shifter Dual-ported on-chip SRAM and integrated I/O peripherals—a complete system-on-a-chip Integrated multiprocessing features 240-lead thermally enhanced MQFP_PQ4 package, 225-ball plastic ball grid array (PBGA), 240-lead hermetic CQFP package RoHS compliant packages KEY FEATURES—PROCESSOR CORE 40 MIPS, 25 ns instruction rate, single-cycle instruction execution 120 MFLOPS peak, 80 MFLOPS sustained performance Dual data address generator