Description
Using CP15 Control Register Enabling the Instruction TCM during soft reset Data TCM accesses Instruction TCM accesses 5-2 5-3 5-7 5-8 5-9
Chapter 6
Bus Interface Unit and Write Buffer
6.1 6.2 6.3 6.4 6.5 About the BIU and write buffer 6-2 AHB bus master interface 6-3 Noncached Thumb instruction fetches 6-10 AHB clocking 6-11 The write buffer 6-14
Chapter 7
Coprocessor Interface
7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 About the coprocessor interface 7-2 Coprocessor interface signals 7-3 L
Features
- 8-4
Chapter 9
4U
Debug Support
About the debug interface 9-2 Debug systems 9-4 The JTAG state machine 9-7 Scan chains 9-12 Debug access to the caches 9-18 Debug interface signals 9-20 Determining the core and system state 9-25 Overview of EmbeddedICE-RT 9-26 Disabling EmbeddedICE-RT 9-28 The debug communication channel 9-29 Monitor mode debugging 9-33
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Contents
Ch.
ARM946E-S Datasheet
